The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$AA$ for tunnel oxide, 74 $AA$ for nitride and 25 $AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$ imes$10$^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$ imes$10$^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.