- EEPROM 셀에서 폴리실리콘 플로팅 게이트의 도핑 농도가 프로그래밍 문턱전압에 미치는 영향
- ㆍ 저자명
- 장성근,김윤장,Chang. Sung-Keun,Kim. Youn-Jang
- ㆍ 간행물명
- 전기전자재료학회논문지
- ㆍ 권/호정보
- 2007년|20권 2호|pp.113-117 (5 pages)
- ㆍ 발행정보
- 한국전기전자재료학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{ imes}10^{15}/cm^{2}$.