In this paper, an all Digital Phase-Locked Loop(DPLL) has been propoed, which has reduced the phase error by using a half period sampling in order to improve the performance of the conventional DPLL which tracks the phase of incoming sinusoidal signal once per cycle for the Positive Going Zero crossing(PGZC) of the signal. The proposed DPLL tracks the phase of input signal twice per cycle with two samplers for the PGZC. So the loop has a half reduction of the steady state phase error fluctuation ranges without decreasing the lock-range in a whole, comparing with that of the conventional DPLL. Also, it has been known that the proposed loop is rapidly locked to input signal for the same valves of phase differenc between sucessive samples and quantization level. The analytic results of the proposed loop have been verified by computer simulation for the practically requeired conditions.