This article describes the hardware design scheme of Hamming MAXNET algorithm which is appropriate for binary pattern classification with minimum HD measurement between stimulus vector and storage vector. Circuit integration is profitable to Hamming MAXNET because the structure of hamming network have a few connection nodes over the similar neuro-algorithms. Designed hardware is the two-layered structure composed of hamming network and MAXNET which enable the characteristics of low power consumption and fast operation with biline volgate sensing scheme. Proposed Hamming MAXNET hardware was designed as quantize-level converter for simulation, resulting in the expected binary pattern convergence property.