This paper describes a development of the PLD design tool in considering with a device fitting. To design digital circuit with PLDs, several steps in the developed PLD design tool are needed such as Boolean description step, pin map step, FUSE map and JEDEC steps ... etc. Especially, we have considered the device fitting to design large digital circuits with PLDs developed the device fitting algorithms based on the PLD device fitting and compared with the results of a another PLD design tool(PALASM). Also, we have proved that the developed PLD design tool is successfully implemented by the connection with a PLD writer(ALL-07), in the case of design digital circuits.