This paper presents a new high-level synthesizer for ASIC designs using ASIC library or FPGAs. DAMUL defines the VHDL description for a specified hardware and allocate some VHDL codes, which describe the behavioral specification, to the corresponding hardware before the synthesis. The interconnections are implemented by the multiplexers, and the objective of allocation is the minimization of the number of multiplexers. Also, the dedicated registers is used for global variables, in order to implement the other necessary registers as well as status and control registers. The effectiveness of the proposed system is shown by the synthesis results of benchmark circuits.