The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{ imes}8$ 150Mb/s or $16{ imes}16$ 150Mb/s, the unit switch of $32{ imes}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{ imes}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{ imes}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.