This paper is the part I of the full study about improved structure of fully interconnected ATM switch to develop the small sized switch element and practical implemention of switch network. This part I paper describes about proposed switch structure, performance evaluations and some of considerations to practical implementation. The proposed structure is constructed of two step buffering scheme in a filtered multiplexer. First step buffering is carried out by small sized dedicated buffers located at each input port. And second step buffering is provided by a large sized common buffer at the output port. To control bursty traffic, we use speed up factor in multiplexing and priority polling according to the levels of buffer occupancy. Proposed structure was evaluated by computer simulation with two evaluation points. One is comparision of multiplexing discipline between hub polling and priority polling. The ogher is overall which should be considered to improve the practical implementation.