This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.