A new approach concurrent transistor sizing and buffer insertion for low power optimization is proposed in this paper. The method considers the tradeoff between upsizing transistors and inserting buffers and chooses the solution with the lowest possible power and area cost. It operates by analyzing the feasible region of the cost-delay curves of the unbuffered and buffered circuits. As such the feasible region of circuits optimized by our method is extended to encompass the envelop of cost-delay curves which represent the union of the feasible regions of all buffered ad unbuffered versions of the circuit. The method is efficient and tunable in that optimality can be traded for compute time and as a result it can in theory near optimal results.