In this paper proposed Component Synthesis Algorithm(CSA) for mapping described HDL to RT component of given library. CSA transform I/O variables of HDL and relation of operators to control/data flow graph(CDFG) that consists of graph, reduce the size of graph, compute the cost, the bound, and the method that use compatibility graph(CG), and then mapping to component. Component synthesis used branch-and-bound algorithm. The result that synthesis using CSA algorithm was proved that this result and the cost of the manual were indentified.