Currently NTSC, PAL, and SECOM are widely used for TV broadcasting systems. In Korea, NTSC has been used to reduce transmission bandwidth and broadband flickers using the Interlaced scanning method. Image data in the Interlaced scanning method require De-interlacing compensation for PC-based multimedia applications. The existing compensation algorithms such as ZOI, FOI, and ELA provieds simple computations and effective image compensation while the PSNR is low and horizontal and vertical edges are hardly detected. In this paper, the ADI(Adaptive De-Interlacing) algorithm that can increase PSNR and detect horizontal and vertical edges is proposed and a hardware system is implemented using three ACTEL 1020B FPGA chips. The system consists of the algorithm part implemented using two FPGAs and the memory control part implemented using rest one. Also the system operation is investigated for real time processing.