Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.