The testing processes for VLSI finished devices are considerably complex because they require different types of ATE to be linked together. Due to the interaction effect between two or more linked ATEs, it is difficult to trace down the cause of the unexpected longer ATE setup time and random yields, which frequently occur in the VLSI circuit-testing laboratory. The goal of this paper is to develop and demonstrate the methodology designed to eliminate the possible interaction factors that might affect the random yields and/or unexpected longer setup time as well as increase the productivity. The statistical method such as design of experiment or multivariate analysis cannot be applied to the final testing floor here directly due to the environmental constraints. Expanded product data information (PDI) is constructed by combining product data information and ATE control information. An architecture utilizing expanded PDI is designed, which enables the engineer to conduct statistical approach investigation and reduce the setup time, as well as increase yield.