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Fabrication of Field-Emitter Arrays using the Mold Method for FED Applications
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  • Fabrication of Field-Emitter Arrays using the Mold Method for FED Applications
  • Fabrication of Field-Emitter Arrays using the Mold Method for FED Applications
저자명
Cho. Kyung-Jea,Ryu. Jeong-Tak,Kim. Yeon-Bo,Lee. Sang-Yun
간행물명
Transactions on electrical and electronic materials
권/호정보
2002년|3권 1호|pp.4-8 (5 pages)
발행정보
한국전기전자재료학회
파일정보
정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.