- DDR 알고리즘에 기반한 교착상태배제 래더 다이어그램 설계
- ㆍ 저자명
- 차종호,조광현,Cha. Jong-Ho,Cho. Kwang-Hyun
- ㆍ 간행물명
- 제어·자동화·시스템공학 논문지
- ㆍ 권/호정보
- 2002년|8권 8호|pp.706-712 (7 pages)
- ㆍ 발행정보
- 제어로봇시스템학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.