Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $mu extrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{circ}C$ and it was reoxidized by wet oxidation at $800^{circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{circ}C$. The programming conditions are possible in 11 V, 500 $mu extrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 imes 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 imes 10^{10} extrm{cm}^2$ and $3.7 imes 10^{18}/ extrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3 imes 10^{12} extrm{cm}^2$ but memory charges decreases.