- CeO2Buffer Layer를 이용한 Pt/BLT/CeO2/Si 구조의 특성
- ㆍ 저자명
- 이정미,김경태,김창일
- ㆍ 간행물명
- 전기전자재료학회논문지
- ㆍ 권/호정보
- 2003년|16권 10호|pp.865-870 (6 pages)
- ㆍ 발행정보
- 한국전기전자재료학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.