With an emergence of SOC from developed IC technology, the VLSI design has required the core re-use technique and modular test development. To minimize the cost of testing SOC, an efficient method is required to optimize the test time and area overhead in conjunction for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient design strategy of core test wrapper to achieve the minimum cost for SOC testing. The proposed strategy adopted advantages of traditional methods and more developed to be successfully used in practice.