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서지반출
Analysis of Process Parameters to Improve On-Chip Linewidth Variation
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  • Analysis of Process Parameters to Improve On-Chip Linewidth Variation
  • Analysis of Process Parameters to Improve On-Chip Linewidth Variation
저자명
Jang. Yun-Kyeong,Lee. Doo-Youl,Lee. Sung-Woo,Lee. Eun-Mi,Choi. Soo-Han,Kang. Yool,Yeo. Gi-Sung,Woo. Sang-Gyun,Cho. Han-Ku,Park.
간행물명
Journal of semiconductor technology and science
권/호정보
2004년|4권 2호|pp.100-105 (6 pages)
발행정보
대한전자공학회
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
서지반출

기타언어초록

The influencing factors on the OPC (optical proximity correction) results are quantitatively analyzed using OPCed L/S patterns. ${sigma}$ values of proximity variations are measured to be 9.3 nm and 15.2 nm for PR-A and PR-B, respectively. The effect of post exposure bake condition is assessed. 16.2 nm and 13.8 nm of variations are observed. Proximity variations of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate the OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4, 13.9, and 15.2 nm are observed for the mask mean-to-targets of 0, 2 and 4 nm, respectively. The decrease the OPC grid size from 1 nm to 0.5 nm enhances the correction resolution and the OCV is reduced from 14.6 nm to 11.4 nm. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The critical dimension (CD) uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 9.9 nm and 8.7 nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved. The decrease of OPC grid size is shown to improve not only the proximity correction, but also the uniformity.