As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random This paper proposes and presents a new efficient network architecture for Reflective Memory System (RMS). A time to copy shared-data among nodes effects critically on the entire performance of the RMS. In this paper, the recent researches about the RMS are investigated and compared. The device named Topology Conversion Switch(TCS) is introduced to realize the proposed network architecture. One of the RMS based industrial control networks, Ethernet based Real-time Control Network (ERCnet), is adopted to evaluate the performance of the proposed network architecture for RMS.