With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.