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A Design Evaluation of Strained Si-SiGe on Insulator (SSOI) Based Sub-50 nm nMOSFETs
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  • A Design Evaluation of Strained Si-SiGe on Insulator (SSOI) Based Sub-50 nm nMOSFETs
  • A Design Evaluation of Strained Si-SiGe on Insulator (SSOI) Based Sub-50 nm nMOSFETs
저자명
Nawaz. Muhammad,Ostling. Mikael
간행물명
Journal of semiconductor technology and science
권/호정보
2005년|5권 2호|pp.136-147 (12 pages)
발행정보
대한전자공학회
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.