The round off noise properties of wave digital filters have known and desirable properties in respect to their realization with short coefficient wordlengths. This paper presents the optimal implementation of wave digital filters by employing multiprocessor archtectures in the sense of input sampling rate, the number of processors, and input-output delay. The implementation will be specified by complete circuit diagrams including control signals, and can be applied to an existing silicon complier for VLSI layout generation.