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Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure
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  • Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure
  • Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure
저자명
Koo. Jae-Bon,Ku. Chan-Hoe,Lim. Sang-Chul,Lee. Jung-Hun,Kim. Seong-Hyun,Lim. Jung-Wook,Yun. Sun-Jin,Yang. Yong-Suk,Suh. Kyung-Soo
간행물명
Journal of information display
권/호정보
2006년|7권 3호|pp.27-30 (4 pages)
발행정보
한국정보디스플레이학회
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.