In a power system, an out-of-step condition causes a variety of risk such as serious damage to system elements, tripping of loads and generators, mal-operation of relays, etc. Therefore, it is very important to detect the out-of- step condition and take a proper measure. This paper presents a study on implementation of out-of-step detection algorithm using VHDL(Very high speed Hardware Description Language). The structure of out-of-step detection algorithm is analyzed for development of out-of-step detection relay on the FPGA(Field Programmable Gate Array). The out-of-step algorithm is separated to 4 parts: DFT IP, complex power calculation IP, out-of-step detection IP, control unit. Each parts are developed and simulated by using VHDL.