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A design of a floating point unit with 3 stages for a 3D graphics shader engine
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  • A design of a floating point unit with 3 stages for a 3D graphics shader engine
  • A design of a floating point unit with 3 stages for a 3D graphics shader engine
저자명
Lee. Kwang-Yeob
간행물명
전기전자학회논문지
권/호정보
2007년|11권 4호|pp.358-363 (6 pages)
발행정보
한국전기전자학회
파일정보
정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
서지반출

기타언어초록

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.