In this paper, we propose a new gate modification method using the input vector maximizes the number of gates in WLS within the optimum range of the minimum leakage power. We prove that MLV is not always the optimal solution, and that the leakage power and area can decrease when modifying the gates using the input vector for which the number of gates in WLS is maximized within the optimum range of the minimum leakage power for the circuits applying the IVC technique and gate modification method. Using the proposed method, the gate-level description circuit can be converted to the modified circuit which reduces the leakage power by chip designer, and the modified circuit can be applied without any modification in design flow.