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0.13μm Cu/Low-k 공정 Setup과 수율 향상에 관한 연구
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  • 0.13μm Cu/Low-k 공정 Setup과 수율 향상에 관한 연구
저자명
이현기,장의구,Lee. Hyun-Ki,Chang. Eui-Goo
간행물명
전기전자재료학회논문지
권/호정보
2007년|20권 4호|pp.325-331 (7 pages)
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한국전기전자재료학회
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{mu}m$ FCT device by the optimization of these process conditions.