This paper presents a derating design approach for reliability improvement of a regulator IC. The IC is usually used in SMPS. The main failure mechanism of interest is voltage drop due to the package delamination mainly caused by two stresses, i.e. temperature and current. The lifetime under stresses is modeled as a function of stresses and time using accelerating life testings. Quantitative and qualitative variation in lifetime according to stress variations are investigated using the modeled lifetime. Stress levels would be determined to achieve required reliability levels in the aspect of derating design for reliability.