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A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems
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  • A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems
  • A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems
저자명
Park. Bong-Hyuk,Lee. Kyung-Ai,Hong. Song-Cheol,Choi. Sang-Sung
간행물명
ETRI journal
권/호정보
2007년|29권 4호|pp.421-429 (9 pages)
발행정보
한국전자통신연구원
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
서지반출

기타언어초록

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.