본 논문에서는 일반적인 Folding 구조를 이용한 R-String Folding Block과 Second Folding Block을 제안하여 최대 500Msample/s로 동작하는 ADC를 설계하였다. 제안된 Folding ADC의 R-String Folding Block에서는 상위 4bit를 병렬로 처리하여 디지털 출력을 얻어내며, Second Folding Block에서는 하위 4bit를 새로운 pipeline 방식을 통해 디지털 출력을 얻어낸다. HSPICE 시뮬레이션 과정을 통해 ADC 동작을 확인하였으며 최대 샘플링 주파수인 500Msample/s로 동작할 경우의 평균 전력소모는 1.34mW로 매우 작음을 확인하였다. 램프입력을 인가하면서 디지털 출력이 변할 때의 입력전압을 측정하여 DNL과 INL을 구한 결과 DNL은 $-0.56LSB{sim}0.49LSB$, INL은 $-0.94LSB{sim}0.72LSB$의 특성을 나타내었다. 사용된 MOSFET 파라미터는 MOSIS에서 제공하는 $0.35{mu}m$ 공정 파라미터이다.
We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.
