SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.