This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using $0.18{mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.