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A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop
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  • A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop
  • A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop
저자명
Choi. Moon-Ho,Yang. Byung-Do,Kim. Nam-Soo,Kim. Yeong-Seuk,Lee. Soo-Joo,Na. Kee-Yeol
간행물명
Transactions on electrical and electronic materials
권/호정보
2010년|11권 1호|pp.20-23 (4 pages)
발행정보
한국전기전자재료학회
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정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18;{mu}m$ standard CMOS process, with an AFE core size of $350;{mu}m;{ imes};230;{mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.