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서지반출
A Real-Time Histogram Equalization System with Automatic Gain Control Using FPGA
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  • A Real-Time Histogram Equalization System with Automatic Gain Control Using FPGA
  • A Real-Time Histogram Equalization System with Automatic Gain Control Using FPGA
저자명
Cho. Jung-Uk,Jin. Seung-Hun,Kwon. Key-Ho,Jeon. Jae-Wook
간행물명
KSII Transactions on internet and information systems : TIIS
권/호정보
2010년|4권 4호|pp.633-654 (22 pages)
발행정보
한국인터넷정보학회
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정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
서지반출

기타언어초록

High quality camera images, with good contrast and intensity, are needed to obtain the desired information. Images need to be enhanced when they are dark or bright. The histogram equalization technique, which flattens the density distribution of an image, has been widely used to enhance image contrast due to its effectiveness and simplicity. This technique, however, cannot be used to enhance images that are either too dark or too bright. In addition, it is difficult to perform histogram equalization in real-time using a general-purpose computer. This paper proposes a histogram equalization technique with AGC (Automatic Gain Control) to extend the image enhancement range. It is designed using VHDL (VHSIC Hardware Description Language) to enhance images in real-time. The system is implemented with an FPGA (Field Programmable Gate Array). An image processing system with this FPGA is implemented. The performance of this image processing system is measured.