This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.