This paper shows an effective partitioning of static global row/column buses for tightly coupled 2D mesh-connected small processor arrays ("mesh", for short). With additional O(n/m (n/m + log m)) time slowdown, it enables the mesh of size $m{ imes}m$ with static row/column buses to simulate the mesh of the larger size $n{ imes}n$ with reconfigurable row/column buses ($m{leq}n$). This means that if a problem can be solved in O(T) time by the mesh of size $n{ imes}n$ with reconfigurable buses, then the same problem can be solved in O(Tn/m (n/m + log m)) time on the mesh of a smaller size $m{ imes}m$ without a reconfigurable function. This time-cost is optimal when the relation $n{geq}m$ log m holds (e.g., m = $n^{1-varepsilon}$ for $varepsilon$ > 0).