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Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias
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  • Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias
  • Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias
저자명
Kim. Hye-Won,Kim. Dong-Chul,Eo. Yung-Seon
간행물명
Journal of semiconductor technology and science
권/호정보
2011년|11권 1호|pp.15-22 (8 pages)
발행정보
대한전자공학회
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
서지반출

기타언어초록

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.