- Bi계 ZnO 칩 바리스터의 저온소결과 전기적 특성
- ㆍ 저자명
- 홍연우,신효순,여동훈,김진호,Hong. Youn-Woo,Shin. Hyo-Soon,Yeo. Dong-Hun,Kim. Jin-Ho
- ㆍ 간행물명
- 전기전자재료학회논문지
- ㆍ 권/호정보
- 2011년|24권 11호|pp.876-881 (6 pages)
- ㆍ 발행정보
- 한국전기전자재료학회
- ㆍ 파일정보
- 정기간행물| PDF텍스트
- ㆍ 주제분야
- 기타
The sintering, defect and grain boundary characteristics of Bi-based ZnO chip varistor (1,608 mm size) have been investigated to know the possibility of lowering a manufacturing price by using 100 % Ag inner-electrode. The samples were prepared by general multilayer chip varistor process and characterized by shrinkage, SEM, current-voltage (I-V), admittance spectroscopy (AS), impedance and modulus spectroscopy (IS & MS) measurement. There are no problems to make a chip varistor with 100% Ag inner-electrode in the sintering temperature range of 850~900$^{circ}C$ for 1 h in air. A good varistor characteristics ($V_n$= 9.3~15.4 V, a= 23~24, $I_L$= 1.0~1.6 ${mu}A$) were revealed but formed $Zn_i^{{cdot}{cdot}}$(0.209 eV) as dominant defect, and increased the distributional inhomogeneity and the temperature instability in grain boundary barriers.