This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${mu}m$ CMOS process. The measured duty cycle error is less than ${pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.