H.264/AVC can use three transforms depending on types of residual data which are to be coded. H.264/AVC always executes $4{ imes}4$ DCT transform. In $16{ imes}16$ intra mode only, $4{ imes}4$ Hadamard transform for luma DC coefficients and $2{ imes}2$ Hadamard transform for chroma DC coefficients are performed additionally. Quantization is carried out to achieve further data compression after transform coding is completed. In this paper, the hardware implementation for DCT transform, Hadamard transform and quantization is studied. Especially, the proposed architecture adopting the pipeline technique can output a quantized result per clock cycle after 33-clock cycle latency. The proposed architecture is coded in Verilog-HDL and synthesized using Xilinx 7.1i ISE tool. The operating frequency is 106MHz at SPARTAN3S-1000. The designed IP can process maximum 33-frame at $1920{ imes}1080$ HD resolution.