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Process Optimization for Flexible Printed Circuit Board Assembly Manufacturing
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  • Process Optimization for Flexible Printed Circuit Board Assembly Manufacturing
  • Process Optimization for Flexible Printed Circuit Board Assembly Manufacturing
저자명
Hong. Sang-Jeen,Kim. Hee-Yeon,Han. Seung-Soo
간행물명
Transactions on electrical and electronic materials
권/호정보
2012년|13권 3호|pp.129-135 (7 pages)
발행정보
한국전기전자재료학회
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
서지반출

기타언어초록

A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.