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Some Device Design Considerations to Enhance the Performance of DG-MOSFETs
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  • Some Device Design Considerations to Enhance the Performance of DG-MOSFETs
  • Some Device Design Considerations to Enhance the Performance of DG-MOSFETs
저자명
Mohapatra. S.K.,Pradhan. K.P.,Sahu. P.K.
간행물명
Transactions on electrical and electronic materials
권/호정보
2013년|14권 6호|pp.291-294 (4 pages)
발행정보
한국전기전자재료학회
파일정보
정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.