This paper proposed an $8{ imes}8$ HEVC inverse core transform architecture reusing multipliers. In HEVC core transform, processing of lower size block is identical with even part of upper size block. So an $8{ imes}8$ core transform architecture can process both $8{ imes}8$ and $4{ imes}4$ core transforms. However, when $8{ imes}8$ core transform architecture is exploited, frame processing time doubles in $4{ imes}4$ core transform, since $8{ imes}8$ and $4{ imes}4$ core transforms concurrently process 8 and 4 pixels, respectively. In this paper, a novel inverse core transform architecture is proposed based on multiplier reuse. It runs as an $8{ imes}8$ inverse core transformer or two $4{ imes}4$ inverse core transformer. Its frame processing time is same in $8{ imes}8$ and $4{ imes}4$ core transforms, and reduces gate counts by 12%.