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Fabrication of Sputtered Gated Silicon Field Emitter Arrays with Low Gate Leakage Currents by Using Si Dry Etch
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  • Fabrication of Sputtered Gated Silicon Field Emitter Arrays with Low Gate Leakage Currents by Using Si Dry Etch
  • Fabrication of Sputtered Gated Silicon Field Emitter Arrays with Low Gate Leakage Currents by Using Si Dry Etch
저자명
Cho. Eou Sik,Kwon. Sang Jik
간행물명
Transactions on electrical and electronic materials
권/호정보
2013년|14권 1호|pp.28-31 (4 pages)
발행정보
한국전기전자재료학회
파일정보
정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.