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Warpage Simulation by the CTE mismatch in Blanket Structured Wafer Level 3D packaging
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  • Warpage Simulation by the CTE mismatch in Blanket Structured Wafer Level 3D packaging
  • Warpage Simulation by the CTE mismatch in Blanket Structured Wafer Level 3D packaging
저자명
Kim. Seong Keol,Jang. Chong-Min,Hwang. Jung-Min,Park. Man-Chul
간행물명
한국생산제조시스템학회지
권/호정보
2013년|22권 1호|pp.168-172 (5 pages)
발행정보
한국생산제조시스템학회
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정기간행물|ENG|
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기타
이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.