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Logic circuit design for high-speed computing of dynamic response in real-time hybrid simulation using FPGA-based system
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  • Logic circuit design for high-speed computing of dynamic response in real-time hybrid simulation using FPGA-based system
  • Logic circuit design for high-speed computing of dynamic response in real-time hybrid simulation using FPGA-based system
저자명
Igarashi. Akira
간행물명
Smart structures and systems
권/호정보
2014년|14권 6호|pp.1131-1150 (20 pages)
발행정보
테크노프레스
파일정보
정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.