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Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance
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  • Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance
  • Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance
저자명
Liu. Yu,Zhang. Wei
간행물명
Journal of computing science and engineering
권/호정보
2014년|8권 4호|pp.215-227 (13 pages)
발행정보
한국정보과학회
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정기간행물|ENG|
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이 논문은 한국과학기술정보연구원과 논문 연계를 통해 무료로 제공되는 원문입니다.
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기타언어초록

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.