In this paper, the impact of substrate bias($V_{BS}$) on the zero capacitor RAM(Z-RAM) in n-channel junctionless multiple gate MOSFET(MuGFET) has been analyzed experimentally. Junctionless transistors with fin width of 50nm and 1 fin exhibits a memory window of 0.34V and a sensing margin of $1.8{ imes}10^4$ at $V_{DS}=3.5V$ and $V_{BS}=0V$. As the positive $V_{BS}$ is applied, the memory window and sensing margin were improved due to an increase of impact ionization. When $V_{BS}$ is increased from 0V to 10V, not only the memory window is increased from 0.34V to 0.96V but also sensing margin is increased slightly. The sensitivity of memory window with different $V_{BS}$ in junctionless transistor was larger than that of inversion-mode transistor. A retention time of junctionless transistor is better than that of inversion-mode transistor due to low Gate Induced Drain Leakage(GIDL) current. To evaluate the device reliability of Z-RAM, the shifts in the Set/Reset voltages and current were measured.